San Jose, California – October18, 2024 – Rambus, a leading provider of memory and interface technologies, today announced the industry’s first complete memory interface chipsets for fifth-generation DDR5 RDIMM and next-generation DDR5 Multi-Rank DIMM (MRDIMM). These innovative new products for RDIMM andMRDIMM seamlessly extend DDR5 performance, delivering unparalleled bandwidth and memory capacity for compute-intensive data centers and AI workloads.
Breaking Bandwidth Barriers with DDR5 MRDIMM and RDIMM
The new Rambus chipsets include:
- Gen5 Registered Clock Driver (RCD), enabling RDIMM to operate at 8000 megatransfers per second (MT/s).
- Multiplexed Registered Clock Driver (MRCD) andMultiplexed Data Buffer (MDB), pushing upcoming MRDIMM speeds up to 12,800 MT/s by doubling the bandwidth of the DIMM beyond the native DRAM device speed.
- Second-generation Server Power Management IC (PMIC5030), designed specifically for DDR5RDIMM 8000 and MRDIMM 12800, delivering ultra-high current at low voltage to support higher speeds and more DRAM and logic chips per module.
A Universal Architecture for Flexible Deployment
DDR5 RDIMM 8000 and industry-standard MRDIMM 12800 utilize a common architecture, compatible with various server platforms, enabling flexible and scalable end-user server configurations. The DDR5 RDIMM 8000 chipset includes the Gen5 RCD, PMIC5030, Serial Presence Detect (SPD) hub, and Temperature Sensor (TS)chip. The DDR5 MRDIMM 12800 chipset includes the MRCD and MDB, along with the same PMIC5030, SPD Hub, and TS chips found in RDIMM 8000.
MRDIMM: Doubling Bandwidth with Innovative Design
TheDDR5 MRDIMM 12800 employs a novel and efficient module design that effectively interleaves two data streams by multiplexing two levels of DRAM, resulting in increased data transfer rates and system performance. This doubles the data transfer rate on the host memory bus compared to native DRAM devices, boosting bandwidth while utilizing the samephysical DDR5 RDIMM connections.
This requires an MRCD that can address the two levels of DRAM in alternating clock cycles, as well as an MDB to direct data streams in and out of the correct DRAM devices. Each DDR5 MRDIMM 12800 requires one MRCD and ten MDB chipsto multiplex the memory channels. The MRCD and MDB will also support four-level DDR5 MRDIMM.
A Leap Forward for Data Center Performance
Rambus is committed to pushing the boundaries of memory technology to meet the ever-growing demands of data centers and AI workloads, said Dr.Chakrabarti, Chief Technology Officer at Rambus. Our new DDR5 RDIMM and MRDIMM chipsets deliver unprecedented performance and scalability, enabling our customers to unlock the full potential of DDR5 and drive innovation in the data center.
References:
- Rambus Website: https://www.rambus.com/
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