台积电发布创新封装技术，提升高性能计算与AI芯片性能
2月18日至22日，在国际固态电路会议（ISSCC 2024）上，全球领先的半导体制造商台积电发布了用于高性能计算和人工智能（AI）芯片的全新一代封装技术。
这项技术基于台积电现有的3D封装技术，集成了硅光子技术，旨在改善互联效果、降低功耗。台积电业务开发资深副总裁张晓强表示，这项技术将有助于封装更多高带宽内存（HBM）和Chiplet小芯片，从而提升AI芯片的性能。
传统上，芯片封装采用2D方式，将芯片放置在基板上，然后用导线连接。然而，随着芯片尺寸的不断缩小和性能要求的提高，2D封装技术已无法满足需求。
3D封装技术通过将芯片堆叠起来，可以缩短芯片之间的连接距离，从而减少延迟和功耗。台积电的新一代封装技术在此基础上，进一步整合了硅光子技术。
硅光子技术利用光信号在硅波导中传输数据，具有低损耗、高带宽和低功耗等优点。通过将硅光子技术集成到封装中，台积电可以实现更高速、更低功耗的芯片互联。
张晓强表示，这项新技术将使AI芯片能够封装更多HBM和Chiplet小芯片，从而提升芯片的计算能力和内存带宽。这将为高性能计算和AI应用提供更强大的硬件基础。
台积电的新一代封装技术预计将广泛应用于数据中心、人工智能和高性能计算等领域。随着AI技术的发展，对高性能计算的需求不断增长，台积电的创新封装技术将为行业提供更强大的解决方案。
英语如下：
**Headline:** TSMC Unveils 3D Packaging Advance: Silicon PhotonicsBoosts AI Chip Performance
**Keywords:** 3D packaging, silicon photonics, AI chips
**Body:**
TSMC, the world’sleading semiconductor manufacturer, has unveiled a next-generation packaging technology for high-performance computing and artificial intelligence (AI) chips at the International Solid-State Circuits Conference (ISSCC 2024) held from February 18 to 22.
The technology builds on TSMC’s existing 3D packaging technology and integrates silicon photonics to enhance interconnect performance and reduce power consumption. TSMC’s Senior Vice President of Business Development, Xiaoguang Zhang, said the technology will enable packaging of more high-bandwidth memory (HBM) and chiplets, boosting the performance of AI chips.
Traditionally, chip packaging has been done in a 2D manner, where chips are placed on a substrate and connected with wires. However, as chip sizes shrink and performance demands increase, 2D packaging has become inadequate.
3D packaging addresses this by stacking chips vertically, reducing the interconnect distance between them and thereby cutting downon latency and power consumption. TSMC’s next-generation packaging technology takes this a step further by incorporating silicon photonics.
Silicon photonics uses light signals to transmit data through silicon waveguides, offering advantages such as low loss, high bandwidth, and low power consumption. By integrating silicon photonics into its packaging, TSMC can achieve faster, lower-power chip interconnects.
According to Zhang, the new technology will allow AI chips to package more HBM and chiplets, increasing the chips’ compute capability and memory bandwidth. This will provide a more powerful hardware foundation for high-performance computing and AI applications.
TSMC’s next-generation packaging technology is expected to find wide application in areas such as data centers, artificial intelligence, and high-performance computing. As AI advances and the demand for high-performance computing grows, TSMC’s packaging innovation will provide the industry with a more robust solution.
【来源】https://www.cls.cn/detail/1601181
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